About the Role
The STA Engineer will be responsible for performing static timing analysis on digital ASIC/SoC designs to ensure that timing requirements are met. The role involves setting up and running STA tools, analyzing timing reports, and identifying and fixing timing violations. The ideal candidate should have strong analytical skills and the ability to work with cross-functional teams.
Requirements
B.E./B.Tech or M.E./M.Tech in Electronics/Electrical Engineering or related field. Minimum 4 years of experience in static timing analysis (STA) of digital ASIC/SoC designs. Strong knowledge of timing concepts, such as setup and hold time, clock skew, and timing exceptions. Proficiency in STA tools, such as Synopsys PrimeTime or Cadence Tempus. Familiarity with Verilog and SDC (Synopsys Design Constraints) for defining timing constraints. Experience with timing closure techniques, such as gate sizing and buffer insertion.
About the Company
Semiconductor Jobs India is a leading online recruitment platform dedicated to serving the semiconductor industry in India. Our mission is to bridge the gap between talented professionals and top semiconductor companies, facilitating mutually beneficial connections and driving the growth of the industry.