About the Role
The SoC Full-Chip Floorplan Engineer (Physical Design) will be responsible for developing and implementing the full-chip floorplan for complex SoC designs. The role involves working closely with the SoC architecture team, IP design teams, and other physical design engineers to create an optimized floorplan that meets performance, power, and area targets. The ideal candidate will have a deep understanding of SoC architecture and the ability to create robust and scalable floorplans. They will collaborate with the physical design team to ensure that the floorplan is effectively implemented and integrated with the rest of the physical design flow.
Requirements
B.E./B.Tech or M.E./M.Tech in Electronics/Electrical Engineering or related field. Minimum 8 years of experience in physical design for complex SoCs, with at least 4 years of experience in full-chip floorplanning. Strong expertise in floorplanning methodologies, tools, and best practices. Deep understanding of SoC architecture, hierarchical design, and design for manufacturability (DFM) techniques. Experience with physical design tools, such as Cadence Innovus or Synopsys IC Compiler. Familiarity with scripting languages, such as Tcl or Python, for automation purposes. Excellent problem-solving, communication, and collaboration skills.
About the Company
Semiconductor Jobs India is a leading online recruitment platform dedicated to serving the semiconductor industry in India. Our mission is to bridge the gap between talented professionals and top semiconductor companies, facilitating mutually beneficial connections and driving the growth of the industry.