About the Role
Develop and optimize RTL-to-GDS methodologies for advanced technology nodes (5nm and beyond). Create and maintain design flows that improve PPA (Power, Performance, Area) and reduce time-to-market. Collaborate with EDA vendors to influence tool development and drive early adoption of new features. Guide design teams in best practices for design convergence and closure. Lead efforts in design flow automation and machine learning-based optimization techniques.
Requirements
M.E./M.Tech with 15+ years of experience across the ASIC design flow, from RTL design to physical implementation.
About the Company
Semiconductor Jobs India is a leading online recruitment platform dedicated to serving the semiconductor industry in India. Our mission is to bridge the gap between talented professionals and top semiconductor companies, facilitating mutually beneficial connections and driving the growth of the industry.