About the Role
The DFT Engineer will be responsible for implementing and verifying testability features in digital ASIC/SoC designs. The role involves developing DFT architecture, inserting DFT structures, generating test patterns, and ensuring high test coverage and fault detection. The ideal candidate should have strong problem-solving skills and the ability to collaborate with cross-functional teams.
Requirements
B.E./B.Tech or M.E./M.Tech in Electronics/Electrical Engineering or related field. Minimum 4 years of experience in DFT (Design for Testability) for digital ASIC/SoC designs. Strong knowledge of DFT techniques, such as scan design, BIST, and boundary scan. Proficiency in Verilog, SystemVerilog, and scripting languages (e.g., Perl, Python, Tcl). Familiarity with DFT tools, such as Synopsys DFT Compiler, Mentor Tessent, or Cadence Encounter Test.
About the Company
Semiconductor Jobs India is a leading online recruitment platform dedicated to serving the semiconductor industry in India. Our mission is to bridge the gap between talented professionals and top semiconductor companies, facilitating mutually beneficial connections and driving the growth of the industry.