About the Role
The Analog Layout Engineer will create and optimize layouts for analog circuits in ASIC/SoC designs. The role involves working closely with analog design engineers to understand circuit requirements, creating layouts that meet performance and manufacturability goals, and ensuring the layouts pass DRC and LVS checks. The ideal candidate will have a strong understanding of analog layout techniques and be able to work independently to deliver high-quality layouts. They will collaborate with the analog design team to improve the overall performance and reliability of the analog circuits.
Requirements
B.E./B.Tech or M.E./M.Tech in Electronics/Electrical Engineering or related field. Minimum 4 years of experience in analog layout design for ASIC/SoC. Strong expertise in layout techniques for analog circuits, such as matching, symmetry, and shielding. Proficiency in layout tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Familiarity with design rule checking (DRC) and layout vs. schematic (LVS) techniques. Experience with advanced process nodes and high-speed analog layouts. Knowledge of analog circuit fundamentals and the ability to work closely with analog design engineers. Preferably based in Hyderabad or willing to relocate. |
About the Company
Semiconductor Jobs India is a leading online recruitment platform dedicated to serving the semiconductor industry in India. Our mission is to bridge the gap between talented professionals and top semiconductor companies, facilitating mutually beneficial connections and driving the growth of the industry.